The present disclosure relates generally to memory device testing, and more specifically to memory device test circuits and methods used for determining memory cell faults.
Memory devices, such as static random access memory (SRAM) devices, may experience failure due to issues, such as, process variations. Process variations can occur due to the difficulty in scaling devices, specifically, from random dopant fluctuations resulting in parameter mismatches for transistors used in memory devices. These problems can result in various types of memory cell faults, such as deceptive read destructive faults and low supply data retention faults, for example. Test methods and circuits can be used to detect these faults resulting from failure mechanisms in the memory devices.